The present invention relates to semiconductor switching devices, and more particularly to switching devices for power switching and power amplification applications and methods of forming same.
Power MOSFETs have typically been developed for applications requiring power switching and power amplification. For power switching applications, the commercially available devices are typically DMOSFETs and UMOSFETs. In these devices, one main objective is obtaining a low specific on-resistance to reduce power losses. In a power MOSFET, the gate electrode provides turn-on and turn-off control upon the application of an appropriate gate bias. For example, turn-on in an N-type enhancement mode MOSFET occurs when a conductive N-type inversion-layer channel is formed in the P-type base region (also referred to as xe2x80x9cchannel regionxe2x80x9d) in response to the application of a positive gate bias. The inversion-layer channel electrically connects the N-type source and drain regions and allows for majority carrier conduction therebetween.
The power MOSFET""s gate electrode is separated from the base region by an intervening insulating layer, typically silicon dioxide. Because the gate is insulated from the base region, little if any gate current is required to maintain the MOSFET in a conductive state or to switch the MOSFET from an on-state to an off-state or vice-versa. The gate current is kept small during switching because the gate forms a capacitor with the MOSFET""s base region. Thus, only charging and discharging current (xe2x80x9cdisplacement currentxe2x80x9d) is required during switching. Because of the high input impedance associated with the insulated-gate electrode, minimal current demands are placed on the gate and the gate drive circuitry can be easily implemented. Moreover, because current conduction in the MOSFET occurs through majority carrier transport through an inversion-layer channel, the delay associated with the recombination and storage of excess minority carriers is not present. Accordingly, the switching speed of power MOSFETs can be made orders of magnitude faster than that of bipolar transistors. Unlike bipolar transistors, power MOSFETs can be designed to withstand high current densities and the application of high voltages for relatively long durations, without encountering the destructive failure mechanism known as xe2x80x9csecond breakdownxe2x80x9d. Power MOSFETs can also be easily paralleled, because the forward voltage drop across power MOSFETs increases with increasing temperature, thereby promoting an even current distribution in parallel connected devices.
DMOSFETs and UMOSFETs are more fully described in a textbook by B. J. Baliga entitled Power Semiconductor Devices, PWS Publishing Co. (ISBN 0-534-94098-6) (1995), the disclosure of which is hereby incorporated herein by reference. Chapter 7 of this textbook describes power MOSFETs at pages 335-425. Examples of silicon power MOSFETs including accumulation, inversion and extended trench FETs having trench gate electrodes extending into an N+ drain region are also disclosed in an article by T. Syau, P. Venkatraman and B. J. Baliga, entitled Comparison of Ultralow Specific On-Resistance UMOSFET Structures: The ACCUFET, EXTFET, INVFET, and Conventional UMOSFETs, IEEE Transactions on Electron Devices, Vol. 41, No. 5, May (1994). As described by Syau et al., specific on-resistances in the range of 100-250 xcexcxcexa9cm2 were experimentally demonstrated for devices capable of supporting a maximum of 25 volts. However, the performance of these devices was limited by the fact that the forward blocking voltage must be supported across the gate oxide at the bottom of the trench. U.S. Pat. No. 4,680,853 to Lidow et al. also discloses a conventional power MOSFET that utilizes a highly doped N+ region 130 between adjacent P-base regions in order to reduce on-state resistance. For example, FIG. 22 of Lidow et al. discloses a high conductivity region 130 having a constant lateral density and a gradient from relatively high concentration to relatively low concentration beginning from the chip surface beneath the gate oxide and extending down into the body of the chip.
FIG. 1(d) from the aforementioned Syau et al. article discloses a conventional UMOSFET structure. In the blocking mode of operation, this UMOSFET supports most of the forward blocking voltage across the N-type drift layer, which must be doped at relatively low levels to obtain a high maximum blocking voltage capability, however low doping levels typically increase the on-state series resistance. Based on these competing design requirements of high blocking voltage and low on-state resistance, a fundamental figure-of-merit (FOM) for power devices has been derived which relates specific on-resistance (Ron,sp) to the maximum blocking voltage (BV). As explained at page 373 of the aforementioned textbook to B. J. Baliga, the ideal specific on-resistance for an N-type silicon drift region is given by the following relation:
Ron,sp=5.93xc3x9710xe2x88x929(BV)2.5xe2x80x83xe2x80x83(1) 
Thus, for a device with 60 volt blocking capability, the ideal specific on-resistance is 170 xcexcxcexa9cm2. However, because of the additional resistance contribution from the channel, reported specific on-resistances for UMOSFETs are typically much higher. For example, a UMOSFET having a specific on-resistance of 730 xcexcxcexa9cm2 is disclosed in an article by H. Chang, entitled Numerical and Experimental Comparison of 60V Vertical Double-Diffused MOSFETs and MOSFETs With A Trench-Gate Structure, Solid-State Electronics, Vol. 32, No. 3, pp. 247-251 (1989). However, in this device, a lower-than-ideal uniform doping concentration in the drift region was required to compensate for the high concentration of field lines near the bottom corner of the trench when blocking high forward voltages. U.S. Pat. Nos. 5,637,989, 5,742,076 and 5,912,497 also disclose popular power semiconductor devices having vertical current carrying capability. The disclosures of these patents are hereby incorporated herein by reference.
In particular, U.S. Pat. No. 5,637,898 to Baliga discloses a preferred silicon field effect transistor which is commonly referred to as a graded-doped (GD) UMOSFET. As illustrated by FIG. 3 from the ""898 patent, a unit cell 100 of an integrated power semiconductor device field effect transistor may have a width xe2x80x9cWcxe2x80x9d of 1 xcexcm and comprise a highly doped drain layer 114 of first conductivity-type (e.g., N+) substrate, a drift layer 112 of first conductivity type having a linearly graded doping concentration therein, a relatively thin base layer 116 of second conductivity type (e.g., P-type) and a highly doped source layer 118 of first conductivity type (e.g., N+). The drift layer 112 may be formed by epitaxially growing an N-type in-situ doped monocrystalline silicon layer having a thickness of 4 xcexcm on an N-type drain layer 114 having a thickness of 100 xcexcm and a doping concentration of greater than 1xc3x971018 cmxe2x88x923 (e.g. 1xc3x971019 cmxe2x88x923) therein. The drift layer 112 also has a linearly graded doping concentration therein with a maximum concentration of 3xc3x971017 cmxe2x88x923 at the N+/N junction with the drain layer 114, and a minimum concentration of 1xc3x971016 cmxe2x88x923 beginning at a distance 3 xcexcm from the N+/N junction (i.e., at a depth of 1 xcexcm) and continuing at a uniform level to the upper face. The base layer 116 may be formed by implanting a P-type dopant such as boron into the drift layer 112 at an energy of 100 kEV and at a dose level of 1xc3x971014 cmxe2x88x922. The P-type dopant may then be diffused to a depth of 0.5 xcexcm into the drift layer 112. An N-type dopant such as arsenic may also be implanted at an energy of 50 kEV and at dose level of 1xc3x971015 cmxe2x88x922. The N-type and P-type dopants can then be diffused simultaneously to a depth of 0.5 xcexcm and 1.0 xcexcm, respectively, to form a composite semiconductor substrate containing the drain, drift, base and source layers.
A stripe-shaped trench having a pair of opposing sidewalls 120a which extend in a third dimension (not shown) and a bottom 120b is then formed in the substrate. For a unit cell 100 having a width Wc of 1 xcexcm, the trench is preferably formed to have a width xe2x80x9cWtxe2x80x9d of 0.5 xcexcm at the end of processing. An insulated gate electrode, comprising a gate insulating region 124 and an electrically conductive gate 126 (e.g., polysilicon), is then formed in the trench. The portion of the gate insulating region 124 extending adjacent the trench bottom 120b and the drift layer 112 may have a thickness xe2x80x9cT1xe2x80x9d of about 2000 xc3x85 to inhibit the occurrence of high electric fields at the bottom of the trench and to provide a substantially uniform potential gradient along the trench sidewalls 120a. The portion of the gate insulating region 124 extending opposite the base layer 116 and the source layer 118 may have a thickness xe2x80x9cT2xe2x80x9d of about 500 xc3x85 to maintain the threshold voltage of the device at about 2-3 volts. Simulations of the unit cell 100 at a gate bias of 15 Volts confirm that a vertical silicon field effect transistor having a maximum blocking voltage capability of 60 Volts and a specific on-resistance (Rsp,on) of 40 xcexcxcexa9cm2, which is four (4) times smaller than the ideal specific on-resistance of 170 xcexcxcexa9cm2 for a 60 volt power UMOSFET, can be achieved. Notwithstanding these excellent characteristics, the transistor of FIG. 3 of the ""898 patent may suffer from a relatively low high-frequency figure-of-merit (HFOM) if the overall gate-to-drain capacitance (CGD) is too large. Improper edge termination of the MOSFET may also prevent the maximum blocking voltage from being achieved. Additional UMOSFETs having graded drift regions and trench-based source electrodes are also disclosed in U.S. Pat. No. 5,998,833 to Baliga, the disclosure of which is hereby incorporated herein by reference.
Power MOSFETs may also be used in power amplification applications (e.g., audio or rf). In these applications the linearity of the transfer characteristic (e.g., Id v. Vg) becomes very important in order to minimize signal distortion. Commercially available devices that are used in these power amplification applications are typically the LDMOS and gallium arsenide MESFETs. However, as described below, power MOSFETs including LDMOS transistors, may have non-linear characteristics that can lead to signal distortion. The physics of current saturation in power MOSFETs is described in a textbook by S. M. Sze entitled xe2x80x9cPhysics of Semiconductor Devices, Section 8.2.2, pages 438-451 (1981). As described in this textbook, the MOSFET typically works in one of two modes. At low drain voltages (when compared with the gate voltage), the MOSFET operates in a linear mode where the relationship between Id and Vg is substantially linear. Here, the transconductance (gm) is also independent of Vg:
gm=(Z/L)unsCoxVdxe2x80x83xe2x80x83(2) 
where Z and L are the channel width and length, respectively, uns is the channel mobility, Cox is the specific capacitance of the gate oxide, and Vd is the drain voltage. However, once the drain voltage increases and becomes comparable to the gate voltage (Vg), the MOSFET operates in the saturation mode as a result of channel pinch-off. When this occurs, the expression for transconductance can be expressed as:
gm=(Z/L)unsCox(Vgxe2x88x92Vth)xe2x80x83xe2x80x83(3) 
where Vg represents the gate voltage and Vth represents the threshold voltage of the MOSFET. Thus, as illustrated by equation (3), during saturation operation, the transconductance increases with increasing gate bias. This makes the relationship between the drain current (on the output side) and the gate voltage (on the input side) non-linear because the drain current increases as the square of the gate voltage. This non-linearity can lead to signal distortion in power amplifiers. In addition, once the voltage drop along the channel becomes large enough to produce a longitudinal electric field of more than about 1xc3x97104 V/cm while remaining below the gate voltage, the electrons in the channel move with reduced differential mobility because of carrier velocity saturation.
Thus, notwithstanding attempts to develop power MOSFETs for power switching and power amplification applications, there continues to be a need to develop power MOSFETs that can support high voltages and have improved electrical characteristics, including highly linear transfer characteristics when supporting high voltages.
Integrated power devices according to first embodiments of the present invention utilize Faraday shield layers to improve device characteristics by reducing parasitic capacitance between terminals of the device. In particular, integrated power devices, which may comprise a plurality of field effect transistor unit cells therein, utilize Faraday shield layers to reduce parasitic gate-to-drain capacitance (Cgd) and concomitantly improve high frequency switching performance. Each of these power devices may include a field effect transistor in an active portion of a semiconductor substrate and a gate electrode that is electrically connected to a gate of the field effect transistor. A Faraday shield layer is provided between at least a first portion of the gate electrode and a drain of the field effect transistor in order to capacitively decouple the first portion of the gate electrode from the drain. The gate electrode and drain typically extend adjacent opposing faces of the semiconductor substrate. The Faraday shield layer is preferably electrically connected to a source of the field effect transistor.
Power devices according to the first embodiments may also include a plurality of field effect transistor cells disposed side-by-side in an active portion of a semiconductor substrate. The plurality of field effect transistor cells may include vertical field effect transistor cells that extend between first and second opposing faces of the semiconductor substrate. A Faraday shield layer is provided that extends on a portion of the first face of the semiconductor substrate that is located outside a perimeter of the active portion. A gate electrode of the device is electrically connected to each gate of the plurality of field effect transistor cells. The Faraday shield layer underlies the gate electrode and separates it from a drain of the power device. The gate electrode also extends outside the perimeter of the active portion (containing the transistor cells) in a manner that substantially confines it to within an outer perimeter of the Faraday shield layer. In this manner, the parasitic gate-to-drain capacitance of the power device can be reduced by capacitively decoupling at least a majority portion of the gate electrode from the drain of the device. A source electrode, which is electrically coupled to each source of the plurality of field effect transistor cells, is also electrically connected to the Faraday shield layer. An intermediate electrically insulating layer is disposed between the Faraday shield layer and the gate electrode. The thickness and material characteristics of the intermediate electrically insulating layer influence, among other things, the degree to which the parasitic gate-to-source capacitance of the device is increased by the presence of the Faraday shield layer. In particular, the thickness, layout and material characteristics of the intermediate insulating layer are preferably chosen so that any impairment in switching performance caused by an increase in parasitic gate-to-source capacitance is significantly outweighed by the improvement in switching performance achieved by reduced parasitic gate-to-drain capacitance.
High frequency switching performance is also enhanced by integrating a gate electrode strip line on the semiconductor substrate. The gate electrode strip line preferably has a first end connected to the gate electrode and a second end connected to a gate pad of the power device. The gate pad extends outside the active portion of the semiconductor substrate. The gate electrode strip line is provided to enhance RF switching performance and is patterned to extend opposite the Faraday shield layer, with the intermediate insulating layer extending therebetween. To maintain a low parasitic gate-to-drain capacitance, the gate electrode, gate electrode strip line and gate pad are preferably patterned so that they are at least substantially confined within an outer perimeter of the Faraday shield layer.
According to other aspects of the preferred power devices, the intermediate electrically insulating layer is designed to provide electrostatic discharge (ESD) protection. In particular, the intermediate electrically insulating layer is designed so that the maximum breakdown voltage that the intermediate electrically insulating layer (or regions therein) can support is less than the maximum breakdown voltage that the gate insulator (e.g., gate oxide) can support between the gate(s) and channel region(s) of the power device. To provide this ESD capability, the intermediate electrically insulating layer preferably comprises a plurality of regions of different electrically insulating materials having different breakdown voltage characteristics. These regions may be spaced side-by-side relative to each other. In particular, some of the electrically insulating regions within the intermediate electrically insulating layer may comprise materials that can support high breakdown voltages but preferably have relatively low dielectric constants (to reduce parasitic gate-to-source capacitance). Other insulating regions within the intermediate electrically insulating layer may comprise materials that can only support relatively low breakdown voltages. The electrically insulating regions that can support relatively high and relatively low breakdown voltages will be referred to herein as strong breakdown regions and weak breakdown regions, respectively. The weak breakdown regions, which experience breakdown first in response to excessive voltage spikes that may be caused by ESD events, provide an electrical path for ESD current that is outside the active portion of the power device. These weak breakdown regions may comprise zinc oxide (ZnO). According to these aspects, the gate pad (and/or gate electrode), the weak breakdown regions and the Faraday shield layer collectively form a metal oxide varistor (MOV). The weak breakdown regions may also comprise intrinsic or P-type polycrystalline silicon.
Vertical power devices according to second embodiments of the present invention utilize discontinuous deep trench regions to improve operating performance by, among other things, lowering specific on-state resistance. These vertical power devices include a semiconductor substrate having a first surface thereon and a drift region of first conductivity type (e.g., N-type) therein. For each power device unit cell, a quad arrangement of trenches is provided that extends into the first surface of the semiconductor substrate and defines a drift region mesa that extends between the trenches. A base region of second conductivity type (e.g., P-type) is also provided that extends into the drift region mesa and forms a first P-N rectifying junction therewith. Within each base region, a respective source region is provided. An insulated electrode is provided in each of the trenches. These trench-based insulated electrodes are electrically connected together and to the source region by a source electrode that preferably extends on the first surface. An insulated gate is also provided on the first surface. The insulated gate electrode may be a stripe-shaped electrode that extends on the drift region mesa, and between the trenches.
The quad arrangement of trenches in each unit cell includes a first pair of trenches at a front of the unit cell and a second pair of trenches at a rear of the unit cell, when the device is viewed in transverse cross-section. According to a preferred aspect of these vertical power devices, the source region extends along the first surface in a lengthwise direction from the front to the rear of the device without interruption by the base region. This lack of interruption of the source region by the base region increases the area of the on-state current path. Contact between the source electrode and base region is nonetheless made directly to the base region, which extends along the first surface in the lengthwise direction from a sidewall of a trench in the first pair to a sidewall of an opposing trench in the second pair. A Faraday shield layer may also be provided that extends on the first surface and surrounds the quad arrangement of trenches. A gate electrode strip line (and gate pad) may also be provided on the Faraday shield layer and an intermediate electrically insulating layer may be provided between the Faraday shield layer and the gate electrode strip line. The intermediate electrically insulating layer may be designed to provide electrostatic discharge protection (ESD).
Additional embodiments of the present invention include packaged power devices. According to these embodiments, a packaged power device includes a device package having an electrically conductive flange therein that contains a slot. An electrically conductive substrate is mounted within the slot in the flange and a dielectric layer is provided on the electrically conductive substrate. The electrically conductive substrate may comprise a semiconductor substrate. If a gate electrode strip line is not integrated within the power device in a preferred manner as described above, the gate electrode strip line may be patterned on the dielectric layer so that it extends opposite the electrically conductive substrate. A vertical power MOSFET is also provided within the package and this power MOSFET has a source electrically coupled and mounted to a first portion of the flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of the gate electrode strip line. A drain terminal is also mounted to the flange and is electrically coupled to a drain of the vertical power device. A gate terminal is mounted to the flange and is electrically coupled to a second end of the gate electrode strip line by a gate metal strap. The source of the vertical power MOSFET is preferably connected to the first portion of the flange by a first solder bond and the gate electrode is electrically connected to the first end of the gate electrode strip line by a second solder bond. In this manner, the flange constitutes a source terminal. An LC network may be provided by integrating a capacitor on the electrically conductive substrate along with gate electrode strip line. The capacitor may include a polysilicon capacitor electrode that is electrically connected to the gate electrode strip line, with the polysilicon capacitor electrode, the dielectric layer and the electrically conductive substrate collectively forming a MOS capacitor.
Packaged power transistors according to still further embodiments of the present invention may also include a package with an electrically conductive flange therein that contains a slot. A ceramic substrate may be mounted within the slot and a gate electrode strip line may be patterned on the ceramic substrate. A vertical power MOSFET is also provide within the package and this vertical power MOSFET includes a source that is electrically coupled and mounted to a first portion of the flange extending outside the slot. The gate electrode of the vertical power MOSFET is electrically coupled and mounted to a first end of the gate electrode strip line.
A packaged power transistor may also include a device package having gate and drain terminals and an electrically conductive housing that operates as a source terminal. An electrically conductive plate may be mounted to the electrically conductive housing and a ceramic insulating layer may extend on a surface of the electrically conductive plate. According to a preferred aspect of this embodiment, a gate electrode strip line is provided that extends on the ceramic insulating layer and opposite the electrically conductive plate. A vertical power MOSFET is also provided having a source electrode electrically coupled to the electrically conductive plate and a gate electrode electrically coupled to a first end of the gate electrode strip line. A first electrical connector is also mounted at a first end to the drain terminal of the device package and at a second end to a drain electrode of the vertical power MOSFET. A second electrical connector is also provided. The second electrical connector is mounted to the gate terminal of the device package and to a second end of the gate electrode strip line.
Vertical power devices according to still further embodiments of the present invention include a semiconductor substrate having a drift region of first conductivity type therein extending adjacent a first face thereof. First and second stripe-shaped trenches are provided that extend in parallel and in a first direction across the semiconductor substrate. These trenches are spaced close to each other in order to provide a high degree of charge coupling to an active portion of the substrate. These first and second stripe-shaped trenches are filled with first and second insulated source electrodes. First and second base regions are provided along the length of the first and second trenches. The first and second base regions extend from a sidewall of the first trench to an opposing sidewall of the second trench. First and second source regions are also provided in the first and second base regions, respectively. An insulated gate electrode is provided on the substrate and this gate electrode extends in a second direction across the substrate. The second direction may be orthogonal to the first direction, so that during forward on-state conduction, majority carriers provided by the first and second source regions flow across the first and second base regions in a direction parallel to the closely spaced first and second stripe-shaped trenches.
Additional power devices may also include a semiconductor substrate having a drift region of first conductivity type therein and first and second stripe-shaped trenches that extend in the semiconductor substrate and define a drift region mesa therebetween. First and second insulated source electrodes are also provided in the first and second stripe-shaped trenches, respectively. In addition, a UMOSFET, comprising a third trench that is shallower than the first and second stripe-shaped trenches, is provided in the drift region mesa. This third trench extends between opposing sidewalls of the first and second stripe-shaped trenches. This UMOSFET may also comprise a transition region that defines rectifying and nonrectifying junctions with the base and drift regions, respectively. Base shielding regions may also be provided. These base shielding regions are preferably self-aligned with the opposing sidewalls of the first and second stripe-shaped trenches.
Methods of forming vertical power devices may also include forming first and second deep trenches in a semiconductor substrate having a drift region of first conductivity type therein. This drift region extends into a mesa defined between first and second opposing sidewalls of the first and second deep trenches, respectively. A UMOSFET is formed in the mesa, preferably along with first and second base shielding regions of second conductivity type. These first and second base shielding regions extend into the mesa and are self-aligned with the first and second opposing sidewalls. A step may also be performed to form a transition region of first conductivity type that extends between the drift region and a base region of second conductivity type within the UMOSFET.
In particular, these methods may include implanting base region dopants of second conductivity type into an active portion of a semiconductor substrate having a drift region of first conductivity type therein and then forming a first mask having openings therein on the active portion of the semiconductor substrate. Shielding region dopants of second conductivity type are then implanted into the active portion of the substrate, using the first mask as an implant mask. A step is then performed to drive-in the implanted base and shielding region dopants to define a base region and a plurality of base shielding regions that extend laterally underneath the first mask and vertically through the base region and into the drift region. First and second deep trenches are then etched into the semiconductor substrate to define a drift region mesa therebetween. This etching step is performed using the first mask as an etching mask. First and second insulated source electrodes are then formed in the first and second trenches, respectively. Source region dopants of first conductivity type are implanted into the drift region mesa. These implanted source region dopants are driven-in to define a source region in the base region. A shallow trench is then formed in the drift region mesa. The shallow trench has a sidewall extending adjacent the base and source regions. An insulated gate electrode is formed in the shallow trench and a source electrode is formed that electrically connects the first and second insulated source electrodes, the source region and the base region together.